Generally, a display device (such as a liquid crystal display device and an OLED (organic light emitting diode) display device) requires establishment of synchronization, more particularly, vertical and horizontal synchronizations. The most traditional method for establishing vertical and horizontal synchronizations is to supply a vertical sync (synchronization) signal and a horizontal sync signal. In this architecture, the start of each vertical sync period is indicated by the vertical sync signal and the start of each horizontal sync period is indicated by the horizontal sync signal. In a panel display device, for example, vertical and horizontal synchronizations are achieved by supplying a vertical sync signal and a horizontal sync signal to a display driver which drives a display panel and operating the display driver in synchronization with the vertical sync signal and the horizontal sync signal.
Recent display systems often use an architecture in which specific packets are transmitted to the display driver to indicate starts of vertical sync periods and horizontal sync periods. For example, MIPI DSI (mobile industry processor interface display serial interface) is a typical specification based on such architecture. In the MIPI DSI specification, a Vsync packet is defined as a packet which indicates the start of each vertical sync period and an Hsync packet is defined as a packet which indicates the start of each horizontal sync period. In the present application, a packet which indicates the start of a vertical sync period may be referred to as vertical sync packet and a packet which indicates the start of a horizontal sync period may be referred to as horizontal sync packet. Most typically, an internal vertical sync signal is generated in response to vertical sync packets in the display driver, and an internal horizontal sync signal is generated in response to horizontal sync packets. Circuits integrated in the display driver operate in synchronization with the internal vertical and horizontal sync signals thus generated.
This architecture advantageously reduces the number of signal lines. The configuration in which a vertical and horizontal sync signals are supplied to a display driver, requires signal lines dedicated to supply the vertical and horizontal sync signals, undesirably increasing the number of signal lines. Transmitting vertical and horizontal sync packets indicating the start timing of the vertical and horizontal sync periods by using a data interface in place of the vertical and horizontal sync signals eliminates the need of providing dedicated signal lines, effectively reducing the number of signal lines.
One problem which may occur in synchronization establishment in a display drive is that the synchronization may not be achieved when noise is applied to signal lines related to the synchronization establishment.
For example, FIG. 1 is a timing chart illustrating an example of the operation in which a horizontal sync packet is transmitted over LANE #i in a display system which uses an architecture in which horizontal sync packets are used to establish horizontal synchronization, more specifically, a display system which uses a serial interface supporting the MIPI DSI specification.
A horizontal sync packet is transmitted to the display driver when a horizontal sync period is started. In a typical operation of the display system, when a horizontal sync packet is supplied to the display driver, the internal horizontal sync signal is asserted in synchronization with the horizontal sync packet in the display driver. Circuits integrated in the display driver perform predetermined operations in response to the assertion of the internal horizontal sync signal.
Nevertheless, when the display driver unsuccessfully receives a horizontal sync packet due to an application of high voltage noise to LANE #i, for example, the internal horizontal sync signal is not asserted at appropriate timing and this results in failure of horizontal synchronization. The similar goes for a vertical sync packet. When the display driver unsuccessfully receives a vertical sync packet, this results in failure of vertical synchronization.
When vertical and/or horizontal synchronization is not achieved due to unsuccessful reception of a vertical and/or horizontal sync packet, this may cause disturbance of the image displayed on the display panel. FIG. 2 illustrates one example of the displayed image when vertical and horizontal synchronizations are not successfully established. When an image data packet is not successfully received, the image disturbance is limited to pixels corresponding to the image data packet; however, failure of reception of a vertical and/or horizontal sync packet may undesirably influence on the entire of the displayed image.
The similar goes for an architecture which establishes vertical and horizontal synchronizations by using a vertical sync signal and a horizontal sync signal. When noise is applied to signal lines over which the vertical and horizontal sync signals are transmitted, this may result in failure of vertical and horizontal synchronizations.
As understood from the above, there is a need for suppressing disturbance of the displayed image caused by unsuccessful synchronization establishment.